1 module SRL16E(Q, A0, A1, A2, A3, CLK, D, CE); 2  3 input A0, A1, A2, A3, CLK, D, CE; 4 output Q; 5  6 reg[15:0] shift_reg; 7 reg Q; 8  9 always@(posedge CLK)10 begin11   if (CE)12     shift_reg <= {shift_reg[14:0],D};13 end14 15 always @(A3 or A2 or A1 or A0 or shift_reg)16 begin17 18   case({A3,A2,A1,A0})19     1: Q = shift_reg[1];20 21     2: Q = shift_reg[2];22 23     3: Q = shift_reg[3];24 25     4: Q = shift_reg[4];26 27     5: Q = shift_reg[5];28 29     6: Q = shift_reg[6];30 31     7: Q = shift_reg[7];32 33     8: Q = shift_reg[8];34 35     9: Q = shift_reg[9];36 37     10: Q = shift_reg[10];38 39     11: Q = shift_reg[11];40 41     12: Q = shift_reg[12];42 43     13: Q = shift_reg[13];44 45     14: Q = shift_reg[14];46 47     15: Q = shift_reg[15];48 49     default: Q = shift_reg[0];50 51   endcase52 53 end54 endmodule